Title :
Dynamic clock management for low power applications in FPGAs
Author :
Brynjolfson, Ian ; Zilic, Zeljko
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
Abstract :
Low power techniques employing dynamically controlled clock rates offer potentially powerful energy saving capabilities. In this paper, we consider the application of this low power technique to FPGAs, where we reduce energy waste in clock distributions. We show that current FPGA clock managers are inadequate for use in dynamically controlled systems. We provide an architectural block, the dynamic clock divider, that can be added either internally to clock managers or as user logic, to allow dynamic clock management
Keywords :
clocks; field programmable gate arrays; frequency dividers; low-power electronics; timing circuits; FPGA; architectural block; clock distributions; clock managers; dynamic clock divider; dynamic clock management; dynamically controlled clock rates; energy waste reduction; low power applications; Application software; Capacitance; Circuits; Clocks; Control systems; Dynamic voltage scaling; Energy consumption; Energy management; Field programmable gate arrays; Power system management;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852635
