A programmable analog frequency-locked loop for VCO characterization and test with 8 ppm resolution

This article presents a digitally controlled analog frequency-locked loop used for VCO characterization and test. The proposed scheme allows a frequency tuning better than 8 parts per million (ppm). The AFLL is implemented in 32nm CMOS technology and standard CMOS library cells are used for all the digital blocks. The AFLL comprises a 17-bit frequency counter running at 5GHz, a 1^st order sigma-delta modulator used for dithering the correction signal, a charge-pump and capacitance used as integrator and a VCO. The frequency counter generates a count difference between the VCO clock and a reference clock. This difference is then pulse-density modulated and applied to a charge-pump feeding a capacitor that acts as an integrator. The generated output voltage is applied to the VCO tuning port and adjusts its oscillating frequency accordingly. An offset value added to the frequency difference allows the VCO to settle to a proportional frequency offset. Using this architecture, the VCO frequency can accurately be tuned digitally without having to change the frequency of a reference clock or sweeping its tuning voltage. Hence, the proposed AFLL can serve as a design-for-test (DFT) solution allowing characterization and testing of the VCO in an all-digital environment such as for digital automated test equipment (ATE).