Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI

We have used DES and Reed-Solomon applications to evaluate a dynamically reconfigurable logic engine (DRLE) LSI and have spatially mapped and temporally partitioned these applications into multiple contexts of a DRLE LSI. The evaluation shows that the DRLE improved by more than an order of magnitude over the conventional low-power μP in both performance and energy consumption. We believe DRLE´s scalability against various size applications, which is achieved by dynamic reconfiguration among multiple contexts, will be invaluable for on-chip programmable IP cores in system LSIs