Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics

Using 28nm test chips, we derive signatures for early-life failures (ELF) in both high-K/metal-gate transistors and ultra low-K inter-metal dielectrics. We also demonstrate that the derived ELF signatures can be successfully detected using a clock control technique. Our results can be utilized to overcome scaled-CMOS reliability challenges in several ways: 1. Low-cost ELF detection during on-line operation of robust systems without requiring expensive redundancy-based error detection techniques; 2. Effective ELF screening during production test while reducing stress time and/or stress levels associated with stress tests such as burn-in.