A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

This paper presents an energy/area-efficient forwarded-clock receiver fabricated in a 28nm CMOS process. The receiver consists of 8 data lanes plus one forwarded-clock lane, and adopts a novel all-digital clock and data recovery (CDR) using a delay-locked loop (DLL). The all-digital DLL with calibration can generate accurate multiphase clocks for both duty-cycle correction and the data recovery in the presence of process variations. The all-digital DLL-based CDR can enter into open-loop mode after lock-in to reduce power and eliminate the clock dithering phenomenon. Furthermore, the CDR can re-lock in the closed-loop mode using a proposed update algorithm to track the temperature and voltage variations without disturbing the data recovery. Measurement results show that the receiver can operate at a data rate of 6.4 Gb/s with a BER<;10^-12, consuming 7.5 mW per lane under a 0.85 V power supply. The core receiver occupies an area of 0.02 mm² per lane.