A 5GS/s 4-bit time-based single-channel CMOS ADC for radio astronomy

A 4-bit 65nm time-based analog-to-digital converter (ADC) targeting the next-generation Square Kilometre Array (SKA) is presented. This ADC is composed of an analog voltage-to-time converter (VTC) front end and a digital time-to-digital converter (TDC) back end. The two components can be physically separated to minimize the impact of digital noise from the ADC on high-gain, high-sensitivity receiver chains common in radio telescopes. At a sampling rate of 5 GS/s the ADC consumes 35 mW from a 1 V supply. After calibration, the ADC achieves a peak SNDR of 22.9 dB, SFDR of 34.0 dB and ENOB of 3.5. At the ERBW of 2100 MHz, SNDR is 18.4 dB, SFDR is 22.3 dB and ENOB is 2.8. The resulting worst-case figure of merit is 1.0 pJ/conversion. This is the highest reported sampling rate for a time-based ADC to date.