RFCMOS extension model accurate up to 40 GHz with distributed junction diode

Author

Kuo, Timothy C.

Author_Institution

VLSI Technol., Philips Semicond., San Jose, CA, USA

fYear

2000

fDate

2000

Firstpage

205

Lastpage

208

Abstract

A 0.2 μm RFCMOS extension model valid up to 40 GHz using BSIM3v3 as the core transistor is presented. To account for model accuracy beyond 20 GHz, a distributed junction diode and substrate network model are introduced. Since this model is physically based, a reasonably accurate model can be generated before the S-parameters measurement is available. Therefore, by using this model, the design cycle of RFCMOS circuit can be substantially reduced. In addition, a new approach for extracting parasitic gate resistance has been developed. To account for induced gate noise, a small signal equivalent circuit is used to simulate the noise performance. Excellent agreement is achieved with this noise model

Keywords

CMOS integrated circuits; UHF integrated circuits; equivalent circuits; field effect MIMIC; field effect MMIC; integrated circuit modelling; integrated circuit noise; semiconductor diodes; 0.2 micron; 40 GHz; BSIM3v3; IC design cycle; RFCMOS extension model; distributed junction diode; induced gate noise; noise model; noise performance simulation; parasitic gate resistance extraction; small signal equivalent circuit; substrate network model; CMOS process; CMOS technology; Circuit noise; Frequency; Resistors; Scattering parameters; Semiconductor device modeling; Semiconductor device noise; Semiconductor diodes; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852649

Filename

852649