Title :
Automatic functional model validation between SPICE and Verilog
Author :
Naum, Michael C. ; Inoue, Yoshio
Author_Institution :
ASIC CAD Dev. Group, Mitsubishi Electronics America Inc., Sunnyvale, CA, USA
Abstract :
This paper outlines the development of a validation methodology suitable for testing and qualification of ASIC libraries. In particular this paper outlines a method which uses SPICE models in conjunction with Verilog models to validate the functionality of a Verilog library
Keywords :
SPICE; application specific integrated circuits; circuit analysis computing; integrated circuit modelling; integrated circuit testing; ASIC model libraries; SPICE; Verilog; automatic functional model validation; computer simulation; qualification; testing; Application specific integrated circuits; Automatic testing; Counting circuits; Current supplies; Design automation; Hardware design languages; Libraries; Process design; SPICE; Test pattern generators;
Conference_Titel :
Industry Applications Conference, 1995. Thirtieth IAS Annual Meeting, IAS '95., Conference Record of the 1995 IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-3008-0
DOI :
10.1109/IAS.1995.530422
