Electrical and photonic I/O test and debug

Author

Li, Meng ; Yamaguchi, Takahiro J.

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

2

Abstract

This session addresses recent test challenges associated with high-speed I/Os implemented in electrical and photonic IC forms. In addition to conventional SERDES I/O test challenges, such as transmitter jitter generation and receiver jitter tolerance type tests, stress techniques in loop-back, known-good-die (KGD), and design-validation to debug to high-volume manufacturing, this session will include a discussion about similar photonic transmitter and receiver test and debug challenges. Moreover, this session will also cover the test and debug challenges of CMOS and silicon-photonic integration, either monolithically or heterogeneous, to provide overall cost-power-density-performance trade-offs and optimizations. Issues pertaining to reliability of these systems will also be discussed.

Keywords

CMOS integrated circuits; input-output programs; integrated circuit reliability; integrated circuit testing; integrated optics; program debugging; CMOS integration; KGD; SERDES I-O test challenges; cost-power-density-performance trade-offs; debug challenges; design-validation; electrical IC forms; high-speed I-O; known-good-die; loopback; photonic IC forms; photonic receiver test; photonic transmitter test; receiver jitter tolerance type tests; silicon-photonic integration; stress techniques; transmitter jitter generation; CMOS integrated circuits; Delays; Jitter; Optical transmitters; Photonics; Receivers; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658558

Filename

6658558