Title :
A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction
Author :
Uyttenhove, K. ; Marques, A. ; Steyaert, M.
Author_Institution :
ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
Abstract :
In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (signal to noise plus distortion) is over 30 dB at 500 MHz clock and fIN=141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30 dB. The chip has been processed in a standard 0.35 μm CMOS technology with double poly and occupies an active area of 0.8 mm2
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit stability; error correction; integrated circuit noise; 0.35 micron; 1 GHz; 500 MHz; 6 bit; CMOS; acquisition speed; digital error correction; double poly; flash ADC; meta-stability; sampling frequencies; signal to noise plus distortion; spurious-free dynamic range; Analog-digital conversion; CMOS technology; Clocks; Degradation; Distortion measurement; Dynamic range; Frequency; Noise measurement; Semiconductor device measurement; Signal sampling;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852659
