Title :
A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V
Author :
Taft, Robert C. ; Tursi, Maria Rosaria
Author_Institution :
Nat. Semicond. East Coast Labs., Fuerstenfeldbruck, Germany
Abstract :
A 100-MSPS 8-bit ADC obtains very low supply voltage operation with four circuit techniques: differential T-gate boosting, a unified coarse/fine analog channel with dual gain, a supply independent delay generator, and a delay-lock loop digital output driver. A maximum DNL below 0.5 LSB and 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained down to 2.2 V, 84 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; delay lock loops; driver circuits; low-power electronics; 10 MHz; 2.2 to 3.8 V; 50 MHz; 8 bit; 84 mW; CMOS; DNL; delay-lock loop digital output driver; differential T-gate boosting; effective bits; low supply voltage operation; parametric operation; subranging ADC; supply independent delay generator; unified coarse/fine analog channel; Boosting; CMOS analog integrated circuits; CMOS digital integrated circuits; Capacitors; Clocks; Delay; Driver circuits; Interpolation; Linearity; Low voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852660
