Title :
A 10-bit, 3 V, 100 MS/s pipelined ADC
Author_Institution :
HSC, Analog Devices, Greensboro, NC, USA
Abstract :
The design of a low-power 10-bit, 100 MS/s ADC is presented. The ADC is based on a pipelined architecture in which the number of bits converted per stage and the stage sizes were optimized to simultaneously achieve the desired linearity while minimizing the total power. When operated at 100 MS/s with a 3 V supply the ADC core dissipates 105 mW. The ADC was fabricated in a 0.35 μm double poly CMOS process
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; pipeline processing; 0.35 micron; 10 bit; 105 mW; 3 V; ADC core; double poly CMOS process; linearity; low-power electronics; pipelined ADC; stage sizes; total power minimisation; Application specific integrated circuits; Capacitors; Circuit testing; Error correction; Noise level; Noise reduction; Pipeline processing; Power dissipation; Redundancy; Sampling methods;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852661
