Design methodology of the embedded DRAM with the virtual socket architecture

Author

Kinoshita, M. ; Yamauchi, T. ; Amano, T. ; Dosaka, K. ; Arimoto, K.

Author_Institution

ULSI Dev. Center, Mitsubishi Electr. Corp., Itami, Japan

fYear

2000

fDate

2000

Firstpage

271

Lastpage

274

Abstract

This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology, this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost the same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18 μm embedded DRAM test device and confirmed over 166 MHz operation

Keywords

DRAM chips; circuit CAD; embedded systems; integrated circuit design; memory architecture; 0.18 micron; 166 MHz; array generator technology; automated tools; design turn around time; eDRAM design; embedded DRAM; synchronous circuit design; virtual socket architecture; Application specific integrated circuits; Automatic control; CMOS technology; Circuit synthesis; Circuit testing; Computer architecture; Design methodology; Random access memory; Sockets; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852664

Filename

852664