Low-power technique for on-chip memory using biased partitioning and access concentration

Author

Kawabe, Naoyuki ; Usami, Kimiyoshi

Author_Institution

Semicond. Co., Toshiba Corp., Kawasaki, Japan

fYear

2000

fDate

2000

Firstpage

275

Lastpage

278

Abstract

In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different sizes of two sub-arrays by inserting transfer-gate into a bit-line. When a smaller array is accessed, the larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 codec LSI. Power consumption was reduced by 40%

Keywords

cellular arrays; large scale integration; low-power electronics; semiconductor storage; video codecs; BPAC technique; MPEG4 codec LSI; access concentration; access frequency; biased partitioning; bit-line transfer gate; code motion; instruction memory; low-power technique; memory array; on-chip memory; Batteries; Capacitance; Codecs; Decoding; Digital systems; Energy consumption; Frequency; Large scale integration; MPEG 4 Standard; Packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852665

Filename

852665