DocumentCode
2158945
Title
Defining standard performance levels for power semiconductor devices
Author
Budihardjo, I. ; Lauritzen, P.O. ; Wong, K.Y. ; Darling, R.B. ; Mantooth, H. Alan
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Volume
2
fYear
1995
fDate
8-12 Oct 1995
Firstpage
1084
Abstract
Model validation for power semiconductor devices is classified into five levels with model performance features and applications defined for each level. The five levels for each device correspond to: basic, accurate, thermal, failure and degradation models. Whenever they exist, examples of device models are identified for each power semiconductor device
Keywords
power semiconductor devices; semiconductor device models; standards; accuracy; degradation models; failure models; model validation; power semiconductor devices; standard performance levels; thermal models; Circuit simulation; Circuit synthesis; NIST; Parameter extraction; Power semiconductor devices; Power semiconductor switches; SPICE; Semiconductor optical amplifiers; Thermal degradation; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Industry Applications Conference, 1995. Thirtieth IAS Annual Meeting, IAS '95., Conference Record of the 1995 IEEE
Conference_Location
Orlando, FL
ISSN
0197-2618
Print_ISBN
0-7803-3008-0
Type
conf
DOI
10.1109/IAS.1995.530423
Filename
530423
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