Title :
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%
Author :
Yokoyama, Yuji ; Itoh, Nobutaka ; Katayama, Masahiro ; Takashima, Kazumasa ; Akasaki, Hiroshi ; Kaneda, Masayuki ; Ueda, Toshitsugu ; Tanaka, Yousuke ; Yamasaki, Eiji ; Todokoro, Masaya ; Toriyama, Keinosuke ; Miki, Hiroshi ; Yagyu, Masayoshi ; Kobayashi,
Author_Institution :
Device Dev. Center, Hitachi Ltd., Japan
Abstract :
A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V
Keywords :
DRAM chips; cellular arrays; embedded systems; memory architecture; redundancy; 1.8 V; 18 Mbit; 33 percent; 4.6 ns; 40 Gbit/s; 9 ns; CAS access time; RAS access time; YS merged sense scheme; data-translation rate; embedded DRAM macro; induced noise; memory cell efficiency; multi-word redundancy scheme; noise restraint capacitors; simultaneous wide bandwidth operation; single-side interface architecture; Bandwidth; Capacitance; Capacitors; Content addressable storage; Laboratories; Logic gates; Noise reduction; Propagation delay; Random access memory; Ultra large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852666
