A reconfigurable cube-connected cycles architecture for wafer scale integration

Author

Tzeng, Nian-Feng

Author_Institution

Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

fYear

1991

fDate

29-31 Jan 1991

Firstpage

33

Lastpage

39

Abstract

Proposes a novel reconfigurable architecture for the cube-connected cycles (CCC) implemented by wafer scale integration (WSI) technology. This design is aimed at maintaining the full rigid structure of the CCC in the presence of manufacturing defects. The spare PEs (processing elements), which are added to every building block of the system, can be shared by the PEs in immediate nearby blocks or be used to substitute defective PEs in distant blocks. As a result, the design utilizes spares more effectively than earlier designs in which spares in a block can be used solely by PEs within the same block, resulting in far better yield improvement

Keywords

VLSI; hypercube networks; parallel architectures; pipeline processing; defective PEs; manufacturing defects; processing elements; reconfigurable cube-connected cycles architecture; rigid structure; wafer scale integration; yield improvement; Computer architecture; Fabrication; Hypercubes; Joining processes; Manufacturing processes; Parallel processing; Pipeline processing; Reconfigurable architectures; Switches; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-9126-3

Type

conf

DOI

10.1109/ICWSI.1991.151693

Filename

151693