CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator

Author

Foley, David J. ; Flynn, Michael P.

Author_Institution

Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland

fYear

2000

fDate

2000

Firstpage

371

Lastpage

374

Abstract

This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85°C. The circuits were fabricated on a generic 0.5 μm digital CMOS process

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF oscillators; circuit tuning; clocks; compensation; delay lock loops; frequency synthesizers; mixed analogue-digital integrated circuits; timing circuits; timing jitter; variable-frequency oscillators; 0 to 85 C; 0.5 micron; 2 to 3.3 V; 200 to 500 MHz; 600 MHz to 1.6 GHz; ASIC; CMOS DLL based clock synthesizer; RMS jitter; delay locked loop; digital CMOS process; low jitter clock synthesizer; low voltage clock synthesizer; multiple clock phases; self-correcting DLL; temperature compensated biasing; temperature compensated tunable oscillator; Clocks; Delay; Frequency; Jitter; Oscillators; Phase detection; Phase locked loops; Synthesizers; Temperature; Tunable circuits and devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852688

Filename

852688