• DocumentCode
    2159449
  • Title

    A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology

  • Author

    Anand, Seema Butala ; Razavi, Behzad

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    379
  • Lastpage
    382
  • Abstract
    This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-μm digital CMOS technology, the recovered clock exhibits an RMS jitter of 10.8 ps for a PRBS sequence of length 27-1 while dissipating 50 mW of power from a 3.3-V supply
  • Keywords
    CMOS integrated circuits; application specific integrated circuits; digital communication; optical receivers; phase locked loops; synchronisation; 0.4 micron; 2.5 Gbit/s; 3.3 V; 50 mW; CMOS technology; NRZ data; PLL technique; PRBS sequence; RMS jitter; clock recovery circuit; fibre-optic receivers; phase-locked type; sample/hold phase detector; two-stage ring oscillator; CMOS technology; Capacitance; Circuits; Clocks; Detectors; Optical signal processing; Phase detection; Phase locked loops; Tuning; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-7803-5809-0
  • Type

    conf

  • DOI
    10.1109/CICC.2000.852690
  • Filename
    852690
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2159449