DocumentCode :
2159558
Title :
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration
Author :
Inukai, T. ; Takamiya, M. ; Nose, K. ; Kawaguchi, H. ; Hiramoto, T. ; Sakurai, T.
Author_Institution :
Inst. of Ind. Sci., Tokyo Univ., Japan
fYear :
2000
fDate :
2000
Firstpage :
409
Lastpage :
412
Abstract :
This paper proposes a new device and circuit scheme that drastically suppresses the stand-by leakage current for the deep sub-0.1 μm era while maintaining the circuit speed. Applying boosted gate voltage on the low leakage switches with higher Vth and thicker Tox, extremely low stand-by power for battery type application is achieved, while degradation of circuit performance and an increase of area overhead are sufficiently suppressed. The combination with a negative gate voltage scheme and the application of the boosted voltage scheme to SRAMs are also discussed
Keywords :
MOS digital integrated circuits; VLSI; circuit simulation; integrated circuit reliability; leakage currents; SRAMs; area overhead; battery type application; boosted gate MOS; circuit performance; circuit speed; leakage-free giga-scale integration; negative gate voltage scheme; Circuit optimization; Circuit simulation; Degradation; Leakage current; Low voltage; Subthreshold current; Switches; Switching circuits; Threshold voltage; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
Type :
conf
DOI :
10.1109/CICC.2000.852696
Filename :
852696
Link To Document :
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