Power minimization by simultaneous dual-Vth assignment and gate-sizing

Gate-sizing is an effective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V_th (threshold voltage) CMOS is ideal for leakage power reduction in low voltage circuits. This paper focuses on simultaneous dual-V_th assignment and gate-sizing to minimize the total power dissipation while maintaining high performance. An accurate power dissipation model that includes short-circuit, switching, and leakage power is derived and used in our optimization. Results show that more than 20% and 10% power reductions are achievable for circuits at high and low switching activities, respectively, compared to single low-V_th CMOS circuits while maintaining performance