Title :
CPU controller optimization in HDL logic synthesis
Author_Institution :
Unified Design Syst. Lab., Motorola Inc., Tempe, AZ, USA
Abstract :
We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description
Keywords :
circuit optimisation; hardware description languages; high level synthesis; iterative methods; reduced instruction set computing; CPU controller optimization; HDL logic synthesis; RISC CPU; area efficiency; behavioral description; high-level description language; power optimisation; symbolic state variables; Circuit synthesis; Control system synthesis; Cost function; Counting circuits; Encoding; Hardware design languages; Laboratories; Logic design; Power dissipation; Registers;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606599
