A high performance IIR filter chip and its evaluation system

A highly flexible programmable IIR filter chip has been designed and fabricated to commercial requirements within a collaborative project involving several industrial partners. The device uses 8 highly regular 16 bit array multiplier-accumulators which have been pipelined to achieve an overall computational rate of 30 MHz using a 1 micron gate array process. Most significant bit first arithmetic has been employed to achieve the target 15 MHz sample rate whilst implementing an 8th order filter. The paper reviews the principles behind the filter chip and its architecture, and describes a modular system which has been built to facilitate its demonstration and evaluation