Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems

Author

Wu, Lin ; Jin, Huawen ; Black, William C., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

2000

fDate

2000

Firstpage

447

Lastpage

450

Abstract

This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme

Keywords

circuit noise; circuit simulation; delay lock loops; jitter; nonlinear network analysis; phase locked loops; voltage-controlled oscillators; DLL simulation; PLL simulation; VCO; delay-locked systems; device noise; locked condition; nonlinear behavioral modeling; numerical computation; phase-locked systems; supply coupling effects; unlocked condition; voltage controlled delay line circuits; Circuit noise; Circuit simulation; Computational modeling; Coupling circuits; Delay lines; Phase locked loops; Predictive models; System performance; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852705

Filename

852705