Issues in multi-level cache designs

Due to the rapid growth of processor speeds and the expansion of the application base, multi-level cache hierarchies are becoming more important for microprocessor systems. One classical technique in designing multi-level caches is the subset-rule, with which the cache contents at one level of a hierarchy are maintained as a subset of the next level of the hierarchy. A major benefit of the subset-rule is its conceptual simplicity for cache coherence control. However, in certain systems, conventional subset management may result in higher hardware costs or in unexpected performance losses. In this paper, we investigate these aspects through simulations for a multiprocessor environment. Several alternatives to the conventional subset approach are proposed and evaluated. We also examine some new techniques for managing coherence information at lower costs when very large caches are involved