Determination of optimal sizes for a first and second level SRAM-DRAM on-chip cache combination

In this paper, an SRAM-DRAM combination memory is used as an on-chip cache memory. The SRAM portion is considered to be the first level cache and the DRAM portion is considered to be the second level cache. Curves are derived for the optimal SRAM and DRAM sizes with memory access time optimized. These curves do vary with the amount of fixed on-chip area available, with different cell size ratios of DRAM to SRAM and with varying DRAM access times. The optimal amount of SRAM, or first level cache, is consistently seen to be much smaller then the general trend toward a large first level cache. For instance, if the on-chip area available for cache could contain 256 K of SRAM then only about 16 K of SRAM should exist along with 2.5 M of DRAM as second level cache for optimal usage of that area