Limitations to the size of single-chip electronic neural networks

The authors analyze and quantify the design tradeoffs which will limit the size of single-chip analog neural networks implemented using standard CMOS technology. Issues investigated include the limits imposed by the neural network architectures themselves, and the related effects of processing variations and defects on the ultimate size of manufacturable neural systems. It is shown that neural networks, even if potentially fault-tolerant, will not automatically provide the capability to make limitless large single-chip integrated circuits