Distributed reconfiguration of fault tolerant VLSI multipipeline arrays with constant interstage path lengths

Author

Al-Asaad, Hussain ; Vai, Mankuan ; Feldman, James

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

75

Lastpage

78

Abstract

A new fault tolerant multipipeline array architecture and its diagnosis/reconfiguration algorithm is presented. This multipipeline array design methodology is characterized by constant, fault distribution independent interstage path lengths. Other features include a low hardware overhead and a high survival rate when it is compared to existing approaches

Keywords

VLSI; fault tolerant computing; pipeline processing; reconfigurable architectures; reliability; constant interstage path lengths; diagnosis/reconfiguration algorithm; distributed reconfiguration; fault distribution; fault tolerant VLSI multipipeline arrays; hardware overhead; multipipeline array architecture; multipipeline array design methodology; survival rate; Circuit faults; Design methodology; Fault tolerance; Flip-flops; Integrated circuit interconnections; Logic arrays; Multiprocessor interconnection networks; Pipelines; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331858

Filename

331858