Fault tolerant processor arrays for nonlinear shortest path problem

A scheme is proposed by which nonlinear graph problems can be efficiently solved using processor arrays even in the presence of multiple faults. The fault tolerance capability is achieved using the majority voting approach, and virtually no extra hardware overhead is necessary by maximizing the utilization of the processing elements (PEs). In addition to this, the proposed scheme also allows a significant reduction in the size of the array such that a [3N/5]×N processor array is enough for processing an N×N input data for shortest path problem (SPP). Computation time of the proposed design is bound to 9N-2 for SPP, while it is 5N-4 for non-fault tolerant designs