Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches

Most existing behavioral synthesis systems put emphasis on optimizing area and performance. Only recently has some research been done to consider testability during behavioral synthesis. In our previous work, we integrated hierarchical testability with behavioral synthesis of simple digital data path circuits to synthesize highly testable circuits (S. Bhatia and N.K. Jha, 1994). In the current work, we consider the testability of complete controller and data path during behavioral synthesis. The methods presented can easily handle large and complex behavioral descriptions with loops, conditionals, and allow different scheduling constructs, such as pipelining, multicycling, and chaining. The test set for the combined controller/data path is generated during synthesis in a very short time and near 100% fault coverage is obtained for almost all the synthesized circuits at practically zero overheads