On-chip TEC-QED ECC for ultra-large, single-chip memory systems

Author

Alzahrani, Fahad ; Chen, Tom

Author_Institution

Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

132

Lastpage

137

Abstract

Soft errors resulted from alpha-particle strikes are one of the major factors that reduces the reliability of memory chips. One way to improve reliability of the memory chip is to employ an on-chip code (ECC). This paper presents a triple-error correcting and quadruple-error detecting (TEC-QED) code that is capable of correcting three and detecting four soft errors simultaneously. Its design is based on odd-weight-column SEC-DED code in conjunction with the parity technique. Results show that timing overhead of less than 10 ns can be expected. The proposed code improves the mean time between failure (MTBF) by a factor of 250% when compared to DEC-DED APC and by a factor of 1300% when compared to any SEC code

Keywords

CMOS integrated circuits; alpha-particle effects; circuit reliability; error correction codes; error detection codes; integrated memory circuits; ECC; TEC-QED ECC; alpha-particle strikes; mean time between failure; memory chips; on-chip code; quadruple-error detecting; reliability; single-chip memory systems; timing overhead; triple-error correcting; Availability; Circuit faults; Delay; Employment; Error analysis; Error correction; Error correction codes; Semiconductor device reliability; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331872

Filename

331872