A scalable shared buffer ATM switch embedded SPRAMS

Author

Jeong, Gab Joong ; Shim, Jae Wook ; Lee, Moon Key ; Ahn, Seung Hun

Author_Institution

Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

109

Abstract

This paper describes the architecture of a scalable shared buffer ATM switch and VLSI implementation. It provides scalability in port size and buffer size. The prototype chip has been designed for 4×4 ATM switch which has a shared buffer for 128 ATM cells. It is integrated in 0.6 μm twin well, double-metal, and single-poly CMOS technology. Operating frequency is 80 MHz. Core size is 11×10 mm². It supports 622 Mbps per port

Keywords

CMOS memory circuits; VLSI; asynchronous transfer mode; buffer storage; memory architecture; multimedia communication; random-access storage; real-time systems; 0.6 micron; 622 Mbit/s; 80 MHz; VLSI implementation; buffer size; core size; double-metal technology; embedded SPRAMS; operating frequency; port size; scalable pipelined RAM system; scalable shared buffer ATM switch; single-poly CMOS technology; twin well technology; Asynchronous transfer mode; CMOS technology; Counting circuits; Electronics industry; Moon; Prototypes; Read-write memory; Scalability; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706853

Filename

706853