Efficient timing analysis for CMOS circuit considering data dependent delays

Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS circuits. Most of the previous approaches in detecting long and short sensitizable paths assume that the rising and falling of gate delays are either fixed or bounded. We propose several algorithms to compute the longest and shortest sensitizable path delays based on a data dependent delay model. A proposed algorithm which is based on a combination of modified static (topological) timing analysis and path sensitization techniques seems to offer the best performance. The results obtained have shown to be more accurate than the traditional path sensitization approach based on the bounded delay model