Title :
A fully-integrated low phase-noise nested-loop PLL for frequency synthesis
Author :
Hafez, Amr N. ; Elmasry, M.I.
Author_Institution :
VLSI Res. Group, Waterloo Univ., Ont., Canada
Abstract :
It is greatly beneficial to integrate the VCO. An efficient way to accomplish that is through the help of wide-bandwidth PLLs. This paper presents a simple nested-loop PLL architecture that achieves very wide BW while maintaining the required frequency resolution and spur rejection. The wide-BW loop, including the loop filter, is integrated on a single chip in a 25 GHz bipolar process. The PLL achieves a phase-noise of -100 dBc/Hz at 10 kHz offset from 1 GHz and consumes 9.9 mA from a 3.3 V supply
Keywords :
UHF integrated circuits; application specific integrated circuits; bipolar integrated circuits; frequency synthesizers; integrated circuit noise; phase locked loops; phase noise; voltage-controlled oscillators; 1 GHz; 25 GHz; 3.3 V; 9.9 mA; ASIC; VCO; bipolar process; frequency resolution; frequency synthesis; fully-integrated PLL; loop filter; low phase-noise PLL; nested-loop PLL; spur rejection; wide-bandwidth PLLs; Circuit optimization; Costs; Feedback; Frequency synthesizers; Interference; Phase locked loops; Phase noise; Radio frequency; Steady-state; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852737
