Synchronization of wave-pipelined circuits

We investigate the synchronization schemes of wave-pipelined circuits. Previous analysis of valid clocking in wave-pipelined circuits is discussed and an intentional clock skew is introduced between the input and output registers as a function of the timing parameters of the wave-pipelined circuit, registers, and clock period. It is shown that, a clock skew value can be determined from the circuit information to achieve expected valid clock speed within the range bounded only by the basic timing constraints of wave pipelining. This is illustrated by applying the clock skew models to a 16-bit wave-pipelined adder designed using Wave-pipelined Transmission-Gate Logic (WTGL) technique. The results confirm the timing analysis. General clocking strategies of wave-pipelined systems are also discussed