A self-testing and self-diagnostic systolic array cell for signal processing

A built-in self test (BIST) method for a systolic array controller chip/multiplier-accumulator chip (SAC/MAC) was used to generate the signatures for all combinational blocks of each cell in parallel. The BIST is combined with a scan path design; therefore, all registers in the array cells are connected as a scan chain and all signatures are shifted out by this scan chain to be compared with a previously generated fault-free signature. Thus, the signature generated by the BIST circuitry determines the status of each cell (fault-free or faulty). The self-diagnostic capabilities were then incorporated into the BIST SAC/MAC cell to solve the problem of the long testing time caused by the long time required to scan out the test results when large arrays are used. Although incorporating BIST into the SAC/MAC cell made the array more testable, some redesign had to be done. The major change was using one chip instead of two