• DocumentCode
    2160706
  • Title

    A FPGA architecture for real-time processing of variable-length FFTS

  • Author

    Langemeyer, Stefan ; Pirsch, Peter ; Blume, Holger

  • Author_Institution
    Inst. of Microelectron. Syst., Leibniz Univ., Hannover, Germany
  • fYear
    2011
  • fDate
    22-27 May 2011
  • Firstpage
    1705
  • Lastpage
    1708
  • Abstract
    A new FFT architecture for real-time implementation of large FFTs is presented. The architecture supports both, high throughput and variable-length processing capabilities. The implementation is configurable at run-time, in order to compute power-of-two length ranging from 16 to 2n. It supports efficient integration of data scaling techniques. A radix-23 DIT FFT algorithm is derived, which minimizes the number of multipliers and supports simple reordering.
  • Keywords
    fast Fourier transforms; multiplying circuits; pipeline arithmetic; scaling circuits; FFT architecture; FPGA architecture; data scaling technique; high-throughput variable-length processing; multipliers; radix-23 DIT FFT algorithm; real-time processing; variable-length FFT; Clocks; Computer architecture; Field programmable gate arrays; Pipelines; Random access memory; Real time systems; Throughput; FFT; high-throughput; variable-length;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on
  • Conference_Location
    Prague
  • ISSN
    1520-6149
  • Print_ISBN
    978-1-4577-0538-0
  • Electronic_ISBN
    1520-6149
  • Type

    conf

  • DOI
    10.1109/ICASSP.2011.5946829
  • Filename
    5946829
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2160706