High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization

Author

Takenaka, N. ; Segawa, M. ; Uehara, T. ; Akamatsu, S. ; Matsumoto, M. ; Kurimoto, K. ; Ueda, T. ; Watanabe, H. ; Matsutani, T. ; Yoneda, K. ; Koshio, A. ; Kato, Y. ; Inuishi, M. ; Oashi, T. ; Tsukamoto, K. ; Komori, S. ; Tomita, K. ; Inbe, T. ; Ohsaki, R.

Author_Institution

ULSI Process Technol. Lab., Matsushita Electron. Corp., Kyoto, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

62

Lastpage

63

Abstract

A high density Embedded DRAM technology has been developed with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC/SRAM. This technology includes (1)W/WNx polymetal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-plugged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology realizes both very small. DRAM cell size of 0.29 /spl mu/m SRAM cell size of 2.77 /spl mu/m/sup 2/ on the same die.

Keywords

DRAM chips; copper; integrated circuit metallisation; tungsten; 0.38 micron; 0.42 micron; Cu; Cu dual damascene metallization; LOGIC process; W-Si; W-plugged stacked contact; W/polysilicon gate; disposable BPSG sidewall; embedded DRAM technology; fine pitch interconnect; self-aligned contact; CMOS technology; Contact resistance; Etching; Isolation technology; Logic; MOS devices; Random access memory; Silicides; Silicon compounds; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852770

Filename

852770