A 0.17 /spl mu/m embedded DRAM technology with 0.23 /spl mu/m/sup 2/ cell size and advanced CMOS logic

Author

Wurzer, H. ; Feldner, I. ; Graf, W. ; Curello, G. ; Faul, J. ; Weber, D. ; Kieslich, A.

Author_Institution

Infineon Technol., Dresden, Germany

fYear

2000

fDate

13-15 June 2000

Firstpage

64

Lastpage

65

Abstract

A new 0.17 /spl mu/m embedded DRAM (eDRAM) technology is presented. Basing on a DRAM process with a cell size of 0.23 /spl mu/m/sup 2/ CMOS logic has been improved by introducing a new isolation concept called deep trench isolation and an aggressive device scaling. This is completed by a 6-level AlCu RIE metalization. This concept enables a system-on-a-chip (SOC) solution up to several hundred Mbits DRAM capacity on smallest chip size and highest yield perspectives.

Keywords

CMOS logic circuits; DRAM chips; integrated circuit metallisation; isolation technology; sputter etching; 0.17 micron; AlCu; AlCu multilevel metallization; CMOS logic; deep trench isolation; device scaling; embedded DRAM technology; reactive ion etching; system-on-a-chip; CMOS logic circuits; CMOS technology; Costs; Diffusion tensor imaging; Etching; Isolation technology; Logic devices; Random access memory; System-on-a-chip; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852771

Filename

852771