Title :
0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI
Author :
Hannon, R. ; Iyer, S.S.K. ; Sadana, D. ; Rice, J.P. ; Ho, H.L. ; Khan, B.A. ; Iyer, S.S.
Author_Institution :
Microelectron Div., IBM Corp., Hopewell Junction, NY, USA
Abstract :
The successful fabrication of commodity 64 Mb DRAM chips and logic device and circuits on patterned SOI wafers is reported for the first time. The effect of SIMOX implantation and annealing on DRAMs in patterned SOI wafers is studied. Excellent yields and comparable performance of DRAM in bulk regions of the patterned SOI wafers are observed. The logic devices in the adjacent SOI area of the patterned wafer show the expected enhanced drive current. This approach enables SOI based embedded DRAM.
Keywords :
DRAM chips; SIMOX; annealing; field effect logic circuits; integrated circuit technology; silicon-on-insulator; 0.25 micron; 64 Mbit; SIMOX implantation; SOI logic; annealing; embedded DRAM technology; fabrication; patterned SOI wafer; Annealing; Circuits; Fabrication; Logic devices; Microelectronics; Power generation; Power supplies; Random access memory; Silicon on insulator technology; System-on-a-chip;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852772
