Dual-metal gate technology for deep-submicron CMOS transistors

Author

Qiang Lu ; Yee Chia Yeo ; Ranade, P. ; Takeuchi, H. ; Tsu-Jae King ; Chenming Hu ; Song, S.C. ; Luan, H.F. ; Dim-Lee Kwong

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2000

fDate

13-15 June 2000

Firstpage

72

Lastpage

73

Abstract

Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.

Keywords

CVD coatings; MOSFET; carrier mobility; rapid thermal processing; semiconductor device metallisation; C-V characteristics; Mo; N-MOSFET; P-MOSFET; Si/sub 3/N/sub 4/; Si/sub 3/N/sub 4/ gate dielectric; Ti; carrier mobility; deep submicron CMOS transistor; dual metal gate technology; fabrication; quantum mechanical effects; rapid thermal chemical vapor deposition; self-aligned process; CMOS process; CMOS technology; Capacitance-voltage characteristics; Chemical processes; Chemical technology; Dielectric devices; Displays; Electrodes; MOSFET circuits; Predictive models;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852774

Filename

852774