Title :
A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM
Author :
Radens, C.J. ; Gruening, U. ; Mandelman, J.A. ; Seitz, M. ; Lea, D. ; Casarotto, D. ; Clevenger, L. ; Nesbit, L. ; Malik, Rohit ; Halle, Sylvain ; Kudelka, S. ; Tews, H. ; Divakaruni, R. ; Sim, Jae-Yoon ; Strong, A. ; Tibbel, D. ; Arnold, Norbert ; Bukofs
Author_Institution :
Semicond. R&D Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
A 0.135 /spl mu/m/sup 2/ trench-capacitor DRAM cell with a trench-sidewall vertical-channel array device has been fabricated using 150 nm groundrules and optical lithography. This 6F/sup 2/ cell features a novel active area layout, a trench-top-oxide (TTO) isolation between trench capacitor and trench gate, maskless self-aligned buried strap node contact, shallow trench isolation (STI), a self-aligned poly-plug bit contact, and two levels of bitline interconnect, both formed using a W dual-damascene process.
Keywords :
DRAM chips; integrated circuit metallisation; isolation technology; 150 nm; 16 Gbit; 4 Gbit; 6F/sup 2/ trench-sidewall vertical-channel array device; W; W dual-damascene process; bitline interconnect; maskless self-aligned buried strap node contact; optical lithography; self-aligned poly-plug bit contact; shallow trench isolation; trench-capacitor DRAM cell; trench-top-oxide isolation; Area measurement; Artificial intelligence; Capacitors; Isolation technology; Maintenance; Oxidation; Paper technology; Random access memory; Time measurement; Very large scale integration;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852777
