POWER2 architecture and performance

Author

Hannon, E.L. ; O´Connell, F.P. ; Shieh, L.J.

Author_Institution

IBM Corp., Austin, TX, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

336

Lastpage

339

Abstract

We briefly describe key features of the POWER2 architecture and the xlf compiler. Using FORTRAN loops and compiler generated instructions, we show how the compiler schedules instructions to make full use of new features of the POWER2 architecture. These loops are two of the most widely used scientific/engineering constructs. They demonstrate the ease with which one can attain near-peak or peak performance on the POWER2 architecture. Finally, we demonstrate the effect of these performance enhancements on several real applications

Keywords

FORTRAN; performance evaluation; program compilers; reduced instruction set computing; scheduling; FORTRAN loops; POWER2 architecture; compiler generated instructions; engineering constructs; instruction scheduling; loops; peak performance; performance; performance enhancements; scientific constructs; xlf compiler; Assembly; Bandwidth; Clocks; Hardware; Power engineering and energy; Power generation; Power system modeling; Reduced instruction set computing; Registers; Scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331920

Filename

331920

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2161452