Testability analysis for test generation in synchronous sequential circuits

Due to the complexity of test generation for stuck-at-faults in synchronous sequential circuits and the permanently increasing problem-size, algorithms solving this problem cannot work with acceptable CPU-time, even on computer systems with very high performance. Relating to this context this paper presents a new testability analysis guiding algorithms for sequential test generation. This testability analysis consists of two separated parts: First, a new technique for the detection of untestable stuck-at-faults; second, heuristics used to guide the decision process in test generation algorithms. Experimental results of sequential benchmark circuits allow us to conclude that our testability analysis provides less CPU-time for sequential test generation than other well-known testability analysis tools