Path-delay fault simulation for a standard scan design methodology

In spite of using scan designs, there remain serious problems concerning the generation and confirmation of test vectors for potential timing problems. Most of the available test generators and the only fault simulators reported for path-delay faults in scan designs rely upon the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. This paper describes a path-delay fault simulator for standard scan environments, based on the parallel-pattern-single-fault-propagation technique