A new cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

Author

Itoh, H. ; Tsunemine, Y. ; Yutani, A. ; Okudaira, T. ; Kashihara, K. ; Inuishi, M. ; Yamamuka, M. ; Kawahara, T. ; Horikawa, T. ; Ohmori, T. ; Satoh, S.

Author_Institution

ULSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

106

Lastpage

107

Abstract

A scalable pedestal cell technology has been successfully developed for the BST capacitor by introducing the damascene scheme into the pedestal electrode formation and by employing [Pt-Ir] alloy for coating the pedestal electrode. With a PVD-BST liner as the blanket nucleating layer and as the barrier layer against the destructive oxidant, the MOCVD-BST functions in prime condition on the storage node developed.

Keywords

barium compounds; capacitors; electrodes; iridium alloys; platinum alloys; strontium compounds; BST capacitor; BaSrTiO/sub 3/; MOCVD-BST; PVD-BST liner; Pt-Ir; Pt-Ir alloy coating; barrier layer; blanket nucleating layer; damascene pedestal electrode; scalable cell technology; Binary search trees; Capacitance; Capacitors; Cities and towns; Coatings; Dielectric losses; Electric breakdown; Electrodes; Research and development; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852788

Filename

852788