Latch design for transient pulse tolerance

Previous work on radiation hardening has focused on designing memory elements to tolerate direct hits by high energy particles. The study of latch designs to tolerate high energy particle induced transient pulses arising in the combinational part of the circuit and traveling to the inputs of DFFs has been, ignored. In this work, we look at ways to slow down the input stage of latches by inserting resistances to tolerate transient pulses. Fault injection experiments indicates that most of the transient pulses can be tolerated with 7.5 ns penalty in performance, at least for the ISCAS-89 benchmark circuits. In circuits for critical systems, this penalty may be acceptable. Furthermore, this is not the best case penalty since the DFF can be individually optimized for the circuit and the transient pulse width can be somewhat shortened through redesign. Therefore, this is a viable approach for tolerating transient pulses in VLSI circuits used in critical systems