Current sensing differential logic (CSDL) for low-power and high-speed systems

Author

Park, Joonbae ; Lee, Jeongho ; Kim, Wonchan

Author_Institution

Integrated Syst. Lab., Seoul Nat. Univ., South Korea

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

129

Abstract

A new low-power high-speed glitch-free logic concept, Current Sensing Differential Logic (CSDL), is presented. This concept is developed for complex integrated systems of prime importance where the reliability in operation and design flexibility. These performance improvements of power and speed are enabled by restricting the internal voltage swings in the logic evaluation tree. Using the CSDL logic, a 64-bit carry lookahead adder is designed in a 0.6 μm CMOS technology. The results of the post-layout simulation show that it achieves 2.9 ns delay with the power consumption of 21 mW at 50 MHz with clock buffer

Keywords

CMOS logic circuits; adders; carry logic; logic design; 0.6 micron; 2.9 ns; 21 mW; 50 MHz; CMOS technology; CSDL; carry lookahead adder; current sensing differential logic; glitch-free logic; high-speed systems; low-power operation; CMOS logic circuits; Clocks; Delay; Energy consumption; Logic design; Logic devices; MOS devices; Switches; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706858

Filename

706858