• DocumentCode
    2162045
  • Title

    A 180 nm copper/low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications

  • Author

    Yeap, G.C.-F. ; Nkansah, F. ; Chen, J. ; Jallepalli, S. ; Pham, D. ; Lii, T. ; Nangia, A. ; Le, P. ; Hall, D. ; Menke, D. ; Sun, J. ; Das, A. ; Gilbert, P. ; Huang, F. ; Sturtevant, J. ; Green, K. ; Lu, J. ; Benavidas, J. ; Banks, E. ; Chung, J. ; Lage, C

  • Author_Institution
    Digital DNA Labs., Motorola Inc., Austin, TX, USA
  • fYear
    2000
  • fDate
    13-15 June 2000
  • Firstpage
    150
  • Lastpage
    151
  • Abstract
    We report a 180 nm CMOS technology with dual gate oxide (DGO) optimized for low power and low cost consumer wireless products. To minimize cost and maximize manufacturability, super halo is used for the first time to integrate 70 /spl Aring/ 2.5-3.3 V I/O devices with either 130 nm/29 /spl Aring/ or 150 nm/35 /spl Aring/ low leakage (LL) p/spl Aring///spl mu/m devices, eliminating three normally-required masks. Core LL devices optimized for 1.5 V and 1.8 V are available to maximize circuit design compatibility and IP reuse. Both LL devices yield superior performance, and less I/sub on//I/sub off/ sensitivity vs. gate-length control for robust manufacturing as compared to recently reported LL devices. This technology also features an all-layer copper/low-k interlayer dielectric backend for speed improvement and dynamic power reduction.
  • Keywords
    CMOS analogue integrated circuits; cellular radio; integrated circuit interconnections; ion implantation; low-power electronics; masks; 1.5 V; 1.8 V; 180 nm; Cu; I/O devices; IP reuse; cell phones; channel doping increase; circuit design compatibility; consumer wireless products; copper/low-k CMOS technology; core LL devices; dual gate oxide; dynamic power reduction; low cost; low power; low-k interlayer dielectric backend; manufacturability; optimization; process integration; robust manufacturing; self-aligned tilt halo implants; super halo; CMOS technology; Circuit synthesis; Copper; Cost function; Design optimization; Implants; Manufacturing; Robust control; Sun; Wireless sensor networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
  • Conference_Location
    Honolulu, HI, USA
  • Print_ISBN
    0-7803-6305-1
  • Type

    conf

  • DOI
    10.1109/VLSIT.2000.852805
  • Filename
    852805