DocumentCode
2162061
Title
Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets
Author
Distante, F. ; Sami, M.G. ; Stefanelli, R. ; Gajani, G. Storti
Author_Institution
Dipartimento di Elettronica, Politecnico di Milano, Italy
fYear
1991
fDate
29-31 Jan 1991
Firstpage
113
Lastpage
119
Abstract
A novel digital architecture supporting implementation of feedforward, multilayered artificial neural networks is presented. Based on a switched bus array philosophy, particular care is taken to minimize area requirements while maximizing throughput and parallelism. The architecture is well suited to support, with minimal additional changes, fault/defect tolerance with respect to faults located in the PEs (processing elements), switches, or buses
Keywords
VLSI; fault tolerant computing; neural nets; parallel architectures; WSI implementation; area requirements; digital architecture; fault tolerant characteristics; linear array architecture; multilayered artificial neural networks; neural nets; parallelism; processing elements; switched bus array philosophy; throughput; Artificial neural networks; Circuit faults; Fault tolerance; Neural networks; Neurons; Production; Robustness; Signal processing; Silicon; Strips;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9126-3
Type
conf
DOI
10.1109/ICWSI.1991.151704
Filename
151704
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